A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference-Reference-Cited by-同舟云学术

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

Published:2023-08-10 Issue:9 Volume:6 Page:680-693
ISSN:2520-1131
Container-title:Nature Electronics
language:en
Short-container-title:Nat Electron

Author:

Le Gallo Manuel^ORCID,Khaddam-Aljameh Riduan,Stanisavljevic Milos,Vasilopoulos Athanasios^ORCID,Kersting Benedikt,Dazzi Martino,Karunaratne Geethan^ORCID,Brändli Matthias,Singh Abhairaj,Müller Silvia M.,Büchel Julian,Timoneda Xavier,Joshi Vinay^ORCID,Rasch Malte J.^ORCID,Egger Urs,Garofalo Angelo,Petropoulos Anastasios^ORCID,Antonakopoulos Theodore^ORCID,Brew Kevin^ORCID,Choi Samuel,Ok Injo,Philip Timothy,Chan Victor,Silvestre Claire,Ahsan Ishtiaq,Saulnier Nicole,Narayanan Vijay,Francese Pier Andrea,Eleftheriou Evangelos,Sebastian Abu^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Instrumentation,Electronic, Optical and Magnetic Materials

Link

https://www.nature.com/articles/s41928-023-01010-1.pdf

Reference55 articles.

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2. Shafiee, A. et al. ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. in 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) 14–26 (IEEE Press, 2016).

3. Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R. & Eleftheriou, E. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 15, 529–544 (2020).

4. Yu, S., Jiang, H., Huang, S., Peng, X. & Lu, A. Compute-in-memory chips for deep learning: recent trends and prospects. IEEE Circuits Syst. Magazine 21, 31–56 (2021).

5. Lanza, M. et al. Memristive technologies for data storage, computation, encryption, and radio-frequency communication. Science 376, eabj9979 (2022).

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