Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties

Author:

Lee Jang-Sik,Cho Jinhan,Lee Chiyoung,Kim Inpyo,Park Jeongju,Kim Yong-Mu,Shin Hyunjung,Lee Jaegab,Caruso Frank

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science,Biomedical Engineering,Atomic and Molecular Physics, and Optics,Bioengineering

Reference38 articles.

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2. White, M. H., Adams, D. A. & Bu, J. On the go with SONOS. IEEE Circuits Dev. 16, 22–31 (2000).

3. De Blauwe, J. Nanocrystal nonvolatile memory devices. IEEE Trans. Nanotech. 1, 72–77 (2002).

4. Park, Y. et al. Highly manufacturable 32 Gb multi-level NAND flash memory with 0.0098 μm2 cell size using TANOS (Si-Oxide-Al2O3-TaN) cell technology. IEEE International Electron Devices Meeting (IEDM), December 11–13, 2.1 (San Francisco, California, 2006). http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4139311&arnumber=4154319&count=284&index=156 .

5. Liu, Z., Lee, C., Narayanan, V., Pei, G. & Kan, E. C. Metal nanocrystal memories — Part I: Device design and fabrication. IEEE Trans. Electron. Dev. 49, 1606–1613 (2002).

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