Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors-Reference-Cited by-同舟云学术

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors

Published:2024-07 Issue:7 Volume:19 Page:970-977
ISSN:1748-3387
Container-title:Nature Nanotechnology
language:en
Short-container-title:Nat. Nanotechnol.

Author:

Pendurthi Rahul^ORCID,Sakib Najam U,Sadaf Muhtasim Ul Karim^ORCID,Zhang Zhiyu^ORCID,Sun Yongwen^ORCID,Chen Chen,Jayachandran Darsith,Oberoi Aaryan^ORCID,Ghosh Subir^ORCID,Kumari Shalini^ORCID,Stepanoff Sergei P.,Somvanshi Divya^ORCID,Yang Yang^ORCID,Redwing Joan M.^ORCID,Wolfe Douglas E.^ORCID,Das Saptarshi^ORCID

Publisher

Springer Science and Business Media LLC

Link

https://www.nature.com/articles/s41565-024-01705-2.pdf

Reference42 articles.

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2. Mistry, K. et al. A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. In 2007 IEEE International Electron Devices Meeting 247–250 (IEEE, 2007).

3. Natarajan, S. et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size. In 2014 IEEE International Electron Devices Meeting 3.7.1–3.7.3 (IEEE, 2014).

4. Turkot, B., Carson, S. & Lio, A. Continuing Moore’s law with EUV lithography. In 2017 IEEE International Electron Devices Meeting (IEDM) 14.4.1–14.4.3 (IEEE, 2017).

5. Iyer, S. S. Three-dimensional integration: an industry perspective. MRS Bull. 40, 225–232 (2015).

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