RADIX-10 PARALLEL DECIMAL MULTIPLIER

Author:

INGLE MRUNALINI E.1,PANSE TEJASWINI1

Affiliation:

1. Electronics Engineering, Yeshwantrao Chavan College of Engineering, Nagpur, India

Abstract

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a new algorithm decimal multioperand carry-save addition that uses a unconventional decimal-coded number systems. We further detail these techniques and it significantly improves the area and latency of the previous design, which include: optimized digit recoders, decimal carry-save adders (CSA’s) combining different decimal-coded operands, and carry free adders implemented by special designed bit counters.

Publisher

Institute for Project Management Pvt. Ltd

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Radix-10 Multiplier Implementation with Carry Skip Adder Using Verilog;Lecture Notes in Electrical Engineering;2021-09-10

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