Radix-10 Multiplier Implementation with Carry Skip Adder Using Verilog

Author:

Shashikumar M.,Das Bhaskar Jyoti,Talukdar Jagritee,Mummaneni Kavicharan

Publisher

Springer Singapore

Reference9 articles.

1. Sonam N, Pitchai M (2015) Implementation of high speed Radix-10 parallel multiplier using Verilog. IEEE, pp 1–6

2. Schulte J, Erle M (2003) Decimal multiplication via carry-save addition. In: IEEE international conference on applications-specific systems, architectures, and processors, pp 348–358

3. Vazquez A, Antelo E, Montuschi P (2007) A new family of high-performance parallel decimal multipliers. In: 18th IEEE symposium on computer arithmetic, Montpellier, France, pp195–204

4. Erle M, Schulte J, Schwarz E (2005) Decimal multiplication with efficient partial product generation. In: 17th IEEE symposium on computer arithmetic, IEEE computer society, pp 21–28

5. Ingle M, Panse T (2012) Radix-10 parallel decimal multiplier. Int J Electr Signals Syst 1:1–7

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