Superior Quality Low-Temperature Growth of Three-Dimensional Semiconductors Using Intermediate Two-Dimensional Layers
Author:
Affiliation:
1. Department of Electrical Engineering, University of Notre Dame, Notre Dame, Indiana46556, United States
Funder
National Institute of Standards and Technology
Semiconductor Research Corporation
Publisher
American Chemical Society (ACS)
Subject
General Physics and Astronomy,General Engineering,General Materials Science
Link
https://pubs.acs.org/doi/pdf/10.1021/acsnano.2c08987
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3. Gitlin, D.; Vinet, M.; Clermidy, F.Cost Model for Monolithic 3D Integrated Circuits. In 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S); IEEE, 2016; pp 1–2.
4. Bridging the Processor-Memory Performance Gapwith 3D IC Technology
5. Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors
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