Thermal Interface Enhancement via Inclusion of an Adhesive Layer Using Plasma-Enhanced Atomic Layer Deposition-Reference-Cited by-同舟云学术

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Thermal Interface Enhancement via Inclusion of an Adhesive Layer Using Plasma-Enhanced Atomic Layer Deposition

Published:2021-04-29 Issue:18 Volume:13 Page:21905-21913
ISSN:1944-8244
Container-title:ACS Applied Materials & Interfaces
language:en
Short-container-title:ACS Appl. Mater. Interfaces

Author:

Kwon Heungdong¹^ORCID,Perez Christopher¹^ORCID,Kim Hyojin K.¹,Asheghi Mehdi¹,Park Woosung²^ORCID,Goodson Kenneth E.¹³⁴

Affiliation:

1. Department of Mechanical Engineering, Stanford University, Stanford, California 94305, United States

2. Division of Mechanical Systems Engineering, Sookmyung Women’s University, Seoul 04310, South Korea

3. Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, United States

4. Huang Building, Dean’s Office Suite, Stanford, California 94305, United States

Funder

National Research Foundation of Korea

Semiconductor Research Corporation

Division of Electrical, Communications and Cyber Systems

Publisher

American Chemical Society (ACS)

Subject

General Materials Science

Link

https://pubs.acs.org/doi/pdf/10.1021/acsami.0c19197

Reference59 articles.

1. Nanoscale thermal transport

2. Energy dissipation and transport in nanoscale devices

3. Purkl, F.; English, T. S.; Yama, G.; Provine, J.; Samarao, A. K.; Feyh, A.; Kim, B.; O’Brien, G.; Ambacher, O.; Howe, R. T.; Kenny, T. W. Serpentine geometry for en-hanced performance of nanometer-thin platinum bolometers. Transducers and Eurosensors XXVII: The 17th International Conference on Solid-State Sensors, Actuators and Microsystems, TRANSDUCERS and EUROSENSORS 2013, 2013; pp 1507–1510.

4. Khan, A. I.; Brenner, K.; Smithe, K. K.; Mleczko, M. J.; Pop, E. Large Temperature Coefficient of Resistance in Atomically Thin 2D Devices. Device Research Conference - Conference Digest, DRC 2019, 2019; pp 125–126.

5. Impact of Self-Heating Effect on Long-Term Reliability and Performance Degradation in CMOS Circuits

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