In Situ Thermal Atomic Layer Etching for Sub-5 nm InGaAs Multigate MOSFETs
Author:
Affiliation:
1. Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, United States
2. Department of Chemistry, University of Colorado, Boulder, Colorado 80309, United States
Funder
Division of Chemistry
Semiconductor Research Corporation
Lam Research Corporation
Defense Threat Reduction Agency
Publisher
American Chemical Society (ACS)
Subject
Mechanical Engineering,Condensed Matter Physics,General Materials Science,General Chemistry,Bioengineering
Link
https://pubs.acs.org/doi/pdf/10.1021/acs.nanolett.9b01525
Reference35 articles.
1. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
2. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
3. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates
4. Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET
5. Record Maximum Transconductance of 3.45 mS/ for III-V FETs
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