1. Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack;Barral V;IEDM Tech. Dig.,2007
2. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
3. A 22 nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications;Jan C-H;IEDM Tech. Dig.,2012
4. High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability;Suk SD;IEDM Tech. Dig.,2005
5. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling;Bangsaruntip S;IEDM Tech. Dig.,2009