Exploring Circuit Design Topologies for RFETs
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-37924-6_3
Reference34 articles.
1. L. Amarù, P. E. Gaillardon, and G. De Micheli. “Efficient arithmetic logic gates using double-gate silicon nanowire FETs”. In: 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS). June 2013, pp. 1–4. https://doi.org/10.1109/NEWCAS.2013.6573572.
2. S. Blawid, D. L. M. de Andrade, S. Mothes, and M. Claus. “Performance Projections for a Reconfigurable Tunnel NanoFET”. In: IEEE Journal of the Electron Devices Society 5.6 (Nov. 2017), pp. 473–479. https://doi.org/10.1109/JEDS.2017.2756040.
3. S. Bobba and G. De Micheli. “Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture”. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23.10 (Oct. 2015), pp. 2103–2115. https://doi.org/10.1109/TVLSI.2014.2358884.
4. Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, and Giovanni De Micheli. “Vertically-stacked Double-gate Nanowire FETs with Controllable Polarity: From Devices to Regular ASICs”. In: Proceedings of the Conference on Design, Automation and Test in Europe. DATE ’13. Grenoble, France: EDA Consortium, 2013, pp. 625–630.
5. Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Amarù, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, and Giovanni De Micheli. “Towards structured ASICs using polarity-tunable Si nanowire transistors”. In: Proceedings of the 50th Annual Design Automation Conference on - DAC ’13 (2013), p. 1. https://doi.org/10.1145/2463209.2488886.
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