Analysis and Comparison of Interface Trap for Single and 3D Stacked Nanowire FET-Reference-Cited by-同舟云学术

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Analysis and Comparison of Interface Trap for Single and 3D Stacked Nanowire FET

Published:2017-10-01 Issue:10 Volume:17 Page:7121-7125
ISSN:1533-4880
Container-title:Journal of Nanoscience and Nanotechnology
language:en
Short-container-title:j nanosci nanotechnol

Author:

Ko Kyul¹,Son Dokyun¹,Kang Myounggon²,Shin Hyungcheol¹

Affiliation:

1. Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, Korea

2. Department of Electronics Engineering, Korea National University of Transportation, Chungju-City, 380-702, South Korea

Publisher

American Scientific Publishers

Subject

Condensed Matter Physics,General Materials Science,Biomedical Engineering,General Chemistry,Bioengineering

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Investigation and optimization of electrical and thermal performance for 5-nm GAA vertically stacked nanowire FETs;Microelectronics Journal;2020-01

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