Design and Implementation of Enhanced Edge Triggered Flip-Flop for Low Power Dissipation

Abstract

Power consumption in integrated circuits is one of the prominent aspects of the design methodologies that affect cost and efficiency. It holds a prominent role in the design and fabrication of Integrated Circuits (ICs). Power consumption in ICs increases largely due to clock diffusion techniques and Flip-Flops (FFs) since they consume a huge amount of power to carry out internal transitions. Various researchers have proposed different flip-flop circuit designs for reducing power consumption in clocking systems. When integrated circuits are operating at high frequency, the clock functions are usually managed using clocked transistors. The increased number of clocked transistors increases power consumption which is a major challenge. This research aims to minimize the power consumption in flip-flops by lowering the number of clock transistors. This paper presents the design of an enhanced Dual Edge Triggered Flip-Flop (2EdTFF) based on ultra-low-power robust pass-transistor logic (PTL) for power consumption reduction. The proposed PTL-based 2EdTFF is implemented and simulated. The results of the simulation analysis show that the transistor count and layout area are reduced for minimizing power consumption. The average power utilization of the proposed approach is 3.69 μW for a power activity of 50%, 25%, and 12.5%. The power utilization of the proposed approach is reduced by 12.6% compared to TGFF, 5.5%, and 6.6% compared to S-TCRFF and TCRFF. Comparative analysis shows that the proposed approach achieves better power reduction with better D-to-Q delay and Power-Delay-Product (PDP) performance.