Abstract
The main idea is to create logic-free vector simulation, based on only read-write transactions on address memory. Stuck-at fault vector simulation is leveraged as a technology for assessing the quality of tests for complex IP-cores implemented in Field Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC). The main task is to implement new simple and reliable models and methods of vector computing based on primitive read-write transactions in the technology of vector flexible interpretive fault simulation. Vector computing is a computational process based on read-write transactions on bits of a binary vector of functionality, where the input data is the addresses of the bits. A vector-deductive method for the synthesis of vectors for propagating input fault lists is proposed, which has a quadratic computational complexity. Analytical expressions of logic that require algorithmically complex computing are replaced by vectors of output states of elements and digital circuits. A new matrix of deductive vectors is synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read–write transaction in memory, exclusion of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on the technological solving of many technical diagnostics problems. A new structure of the sequencer for vector deductive fault simulation is proposed, which is characterized by ease of implementation on a single memory block. It eliminates any traditional logic, uses data read-write transactions in memory to form an output fault vector, uses data as addresses to process the data itself.
Publisher
Research Institute for Intelligent Computer Systems
Subject
Computer Networks and Communications,Hardware and Architecture,Information Systems,Software,Computer Science (miscellaneous)
Cited by
3 articles.
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