Author:
Benini L.,Vuillod P.,Bogliolo A.,Micheli G. De
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Information Systems,Signal Processing
Cited by
14 articles.
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4. A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2012-06
5. Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2011-01