Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01
2. Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05
3. High level fault modeling of analog circuits through automated model generation using Chebyshev and Newton interpolating polynomials;Analog Integrated Circuits and Signal Processing;2014-11-01
4. Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling;Journal of Electronic Testing;2013-08-24
5. Automated Model Generation Algorithm for High-Level Fault Modeling;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2010-07
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