Developing an application for 3D IC chip stacking technology-Reference-Cited by-同舟云学术

Developing an application for 3D IC chip stacking technology

Published:2016 Issue:1 Volume:9 Page:1-14
ISSN:1882-6229
Container-title:Synthesiology
language:en
Short-container-title:Synthesiology

Author:

AOYAGI Masahiro¹,IMURA Fumito¹,KATO Fumiki¹,KIKUCHI Katsuya¹,WATANABE Naoya¹,SUZUKI Motohiro¹,NAKAGAWA Hiroshi¹,OKADA Yoshikuni¹,YOKOSHIMA Tokihiko²,YAMAJI Yasuhiro¹,NEMOTO Shunsuke¹,TUNG Bui Thanh¹,SAMSON Melamed¹

Affiliation:

1. Nanoelectronics Research Institute, AIST

2. Faculty of Science and Engeneering, Waseda University

Publisher

The Editorial Committee of Synthesiology

Link

https://www.jstage.jst.go.jp/article/synth/9/1/9_1/_pdf

Reference12 articles.

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3. [6] K. Takahashi, H. Terao, Y. Tomita, Y. Yamaji, M. Hoshino, T.Sato, T. Morifuji, M. Sunohara and M. Bonkohara: Current status of research and development for three-dimensional chip stack technology, Jpn. J. Appl. Phys., 40, 3032-3037 (2001).

4. [7] J. M. Yannou, “Roadmap Analysis: 3D Wafer Level Packaging”, ESTC2010 Workshop 3D WLP, (2010).

5. [9] M. Kawano, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro and S. Matsui: Three-dimensional packaging technology for stacked DRAM with 3-Gb/s data transfer, IEEE Trans. Electron Devices, 55 (7), 1614 - 1620 (2008).

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