Observation of the Full Interface of Multi-level Interconnects for Sub-Half-Micron Devices

Abstract

1. AbstractIn recent years, the problem of electrical resistance of vias and contact holes has become greater because a thin insulated layer formed at the interface of the hole has become a serious difficulty in the manufacture of ULSIs. In using conventional techniques of cross sectional analysis to examine the cause, only one cross section of the hole can be analyzed, therefore there is the problem that the two-dimensional interface layer formed cannot be analyzed exactly.In this paper, we have developed a new observation method to inspect two dimensions of the layer formed locally at the interface of the holes. This new observation method gives the configuration, coverage, and element map of the interface layer because the full interface of holes can be inspected; therefore, the process margin can be discussed. The present technique is demonstrated in failure analysis of sub-half-micron vias filled with tungsten.