Direct Measurements of Thermal Stress Distributions in Large Die Bonds for Power Electronics

Abstract

ABSTRACTLarge semiconductor devices can be subject to significant mechanical stress resulting from thermal expansion mismatch between the devices and packaging materials. This stress can either cause mechanical failure or change the operational characteristics of the device. Furthermore, this stress governs the reliability of the system during use. Therefore, a complete understanding is required of the nature of stress evolution during packaging, and its time and temperature dependence during subsequent service. In the present investigation, the absolute magnitudes and spatial distributions of time-dependent thermal residual stress are measured directly by piezospectroscopic techniques. These measurements are performed with high stress (±15 MPa) and spatial (1 μm) resolution in silicon specimens attached to substrates. Measurements are performed at room temperature on 25 mm square specimens, with continuous, layered solder joints in model specimens of silicon/solder/copper. Room temperature creep relaxation is also investigated. The stress data are then analyzed according to fundamental micromechanical models.