Modelling Geometrical Effects of Parasitic and Contact Resistance of FET Devices

Abstract

AbstractThe continual trend in decreasing the dimensions of semiconductor devices results in a number of technological problems. One of the more significant of these is the increase in contact resistance, Rc. In order to understand and counteract this increase, Rc needs to be quantitatively modelled as a function of the geometrical and material properties of the contact. However the use of multiple semiconductor layers for ohmic contacts makes the modelling and calculation of Rc a more difficult problem. In this paper, a Tri-Layer Transmission Line Model (TLTLM) is used to analyse a MOSFET ohmic contact and gatedrain region. A quantitative assessment of the influence on Rc of important contact parameters such as the metal-silicide specific contact resistance, the silicide-silicon specific contact resistance and the gate-drain length can thus be made. The paper further describes some of the problems that may be encountered in defining Rc when the dimensions of certain types of contact found in planar devices decrease.