Author:
Doppelt Pascal,Baum Thomas H.
Abstract
In the microelectronics industry, integrated circuit (IC) device performance is continually increasing while the critical feature sizes are rapidly decreasing. Since this trend is expected to continue for future generations of ICs, areal density constraints often require that circuit designs utilize multilevel structures with vertical interconnects. It was recently demonstrated that the resistivity of the metal interconnects may limit device performance in multilevel thin-film structures. Although Al metallurgy (Al/2 wt.% Cu alloy) is extensively used for IC metallization today, lower resistivity metals, such as gold, copper, and silver may be necessary for designs requiring feature sizes of 0.25 μm or less. Chemical vapor deposition (CVD) is an attractive technique for the conformal filling of submicron vertical interconnects. For CVD to be generally applicable to IC fabrication, volatile precursors with adequate stability must be designed and optimized. Lastly, IC metallization typically requires that both uniformity and conformality be achieved simultaneously in a single process step.
Publisher
Springer Science and Business Media LLC
Subject
Physical and Theoretical Chemistry,Condensed Matter Physics,General Materials Science
Cited by
81 articles.
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