Why SiNx:H is the Preferred Gate Dielectric for Amorphous Si Thin Film Transistors (TFTS) and SiO2 is the Preferred Gate Dielectric for Polycrystalline Si TFTs

Abstract

ABSTRACTConstraint theory developed for bulk glasses and recently applied to thin films and single crystalline Si (C-Si) dielectric interfaces is extended in this paper to a-Si:H and polycrystalline-Si (poly-Si) dielectric interfaces in TFTs where it provides guidelines for device optimization. The constraining effects of network bonding forces are a linear function of the average bonding coordination, Nav. Nav ∼ 3 separates low-defect density networks as in Si02 (Nav =2.67), from highly-defective networks such as non-hydrogenated Si3N4 (Nay = 3.43). Nay ∼ 3 also separates device-quality from highly-defective Si-dielectric interfaces. These criteria are applied to Si-Si02 and Si-SiNx:H interfaces that are integral components of TFT devices.