Via-Hole Addressed TFT and Process for Large-Area A-Si:H Electronics

Abstract

ABSTRACTWe demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. All gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 μm in 50 μm glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.