Hall Mobility in Strained SiGe p-Mosfets

Abstract

One of the limiting factors in the performance of future CMOS integrated circuits is the low hole mobility which causes the transconductance of p-channel transistors to be inferior to those of n-channel devices. One promising way of enhancing hole mobility is to introduce a buried SiGe layer under the gate of p-MOS transistors. The mobility improvement thus results from, i) reduction in surface scattering (by moving carriers away from scattering sites at the Si/SiO2 interface), and ii) higher in-plane hole mobility in biaxally strained SiGe layers.