Semiconductor Dopant Profile and Dielectric Characterization with Scanning Capacitance Microscopy

Abstract

ABSTRACTScanning capacitance microscopy (SCM) has been commonly used to image dopant gradients in silicon and other semiconductors. As a mobile, high-resolution (to 10 nm) metal-oxide-semiconductor (MOS) probe, SCM also is a non-destructive, contactless tool with which to examine local variations in dielectric thin film quality and local variations in semiconductor substrate properties. Virtually any measurement that can be made with fabricated metal electrodes can also be made with SCM. Two particular applications being pursued are characterization of high-κ dielectric films on silicon for next generation integrated circuits and characterization of native and deposited insulators on wide bandgap semiconductors.Local differential capacitance (ΔC) versus tip bias (Vdc) measurements can be made with SCM using an ac voltage to generate the differential capacitance signal. These measurements differ from conventional C-V measurements due to the 3-D nature of the scanning capacitance microscope tip and the method used to generate the differential capacitance signal. Theoretical predictions and experimental measurements are made of SCM differential capacitance versus dc bias voltage (ΔC-V) curves for MOS capacitors with various levels of fixed and interface traps. The goal of this work is to determine if quantitative interface trap distributions can be made using SCM and if variations in interface density can be observed near defects or device structures. The response of the SCM MOS capacitance measurement to a local electric field stress and optical pumping from the atomic force microscope (AFM) laser will also be discussed.