Development of 3D-Packaging Process Technology for Stacked Memory Chips-Reference-Cited by-同舟云学术

Development of 3D-Packaging Process Technology for Stacked Memory Chips

Published:2006 Issue: Volume:970 Page:
ISSN:0272-9172
Container-title:MRS Proceedings
language:en
Short-container-title:MRS Proc.

Author:

Mitsuhashi Toshiro,Egawa Yoshimi,Kato Osamu,Saeki Yoshihiro,Kikuchi Hidekazu,Uchiyama Shiro,Shibata Kayoko,Yamada Junji,Ishino Masakazu,Ikeda Hiroaki,Takahashi Nobuaki,Kurita Yoichiro,Komuro Masahiro,Matsui Satoshi,Kawano Masaya

Abstract

ABSTRACTA 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.

Publisher

Springer Science and Business Media LLC

Subject

General Engineering

Reference3 articles.

1. 2. Garrou Philip , “3D Integration: A Status Report” in Proc. 3D Architectures for Semiconductor Integration and Packaging, Tempe, Arizona, June, 2005

2. 1. Takahashi Kenji et al., “Process Integration of 3D Chip Stack with Vertical Interconnection” in Proc. 2004Electronic Components and Technology Conference, pp. 601–609

3. 3. Ikeda H. , Kawano M. and Mitsuhashi T. , “Stacked Memory Chip Technology Development”, SEMI Technology Symposium (STS) 2005 Proceedings, Session 9 pp. 37–42.

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