Assessment of Planarization length variation by the Step-Polish-Response (SPR) Method

Author:

Bartha Johann. W.,Bormann Tilo,Estel Kathrin,Zeidler Dieter

Abstract

AbstractIn spite of the fact, that the main purpose of CMP is the planarization of surfaces, most processes are optimized with respect to the removal rate. This might be due to a lack in techniques for the determination of the planarization behavior. The commonly used expression “Planarization Length” implies a maximum lateral extension over which the planarization is obtained and which can not be improved. Several attempts have been made to determine the planarization length by studying the CMP on different test patterns. The general problem in the interpretation of the data is the interaction of neighboring pattern with different pattern densities. This problem does not apply to the most simple pattern possible, which is a single step with an extension of the up and down areas much larger than the planarization length. In this case the spatial derivative of the resulting contour after CMP is directly the demanding transfer function to be used for the convolution. This concept, initially proposed by Boning et. al., was applied to evaluate the polish of copper and silicon oxide. Wafers with concentrically steps in Cu or SiO2 films with an extension of 1 to 5 cm have been prepared. During polish, the initially infinite steep step widens up, yielding the planarization length as a function of the removal respective the polishing time. Significant differences in the evaluation of the planarization length could be quantified depending on the pad, slurry and tool parameters. Our first experiments revealed a decrease in planarization length by the addition of BTA in a copper slurry. We believe that the SPR method enables a unambiguous, pattern independent determination of the planarization capability in CMP.

Publisher

Springer Science and Business Media LLC

Subject

General Engineering

Reference4 articles.

1. 3. Boning Duane , Chung James , Ouma Dennis , and Divecha Rajesh “Spatial Variations in Semiconductor Processes: Modelling for Control”, ECS Meeting, Montreal, May, 1997

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