Surface planarity and microstructure of low temperature silicon SEG and ELO

Abstract

Surface planarity and epi/SiO2 interface characteristics of selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO), deposited at 800–950 °C/10 or 25 Torr, have been studied for micron-sized structures. SEG at 860 °C showed superior planarity and reduced ratio of facet width to epi thickness, compared to higher deposition temperatures. Data showed that epi/SiO2 interface defects are greatly reduced for structures parallel to (100) and/or by adding HCl to the source gas, compared to interfaces positioned at standard orientation (110) on a (100) substrate. The transition from SEG to ELO in view of the facet orientations will be discussed. To correlate structural with electrical data, n+/p diodes were fabricated on as-grown and polish planarized SEG. Leakage current values of approximately 100 nA/cm2 could be measured. These are comparable to similar n+/p junctions fabricated on conventional epi.