Fabrication and Low Temperature Transport Studies of Sub-Micron, In-Plane Gated Fets Defined by Low Energy Ion Exposure

Author:

Andrews C.C.,Spencer G.F.,Li F.,Weichold M.H.,Kirk W.P.

Abstract

ABSTRACTNanoscale gated quantum wires in GaAs MODFET material with the conduction channel and gates in the plane of the 2DEG have been fabricated and studied. Electron beam lithography was used for mask definition followed by flood exposure to low energy argon ions (150 eV) for pattern transfer into the 2DEG. Compared to metal top-gate designs the in-plane design simplifies fabrication and reduces device capacitance, promising ultra-fast operation. This method of pattern transfer produced devices having channel-to-gate isolation of 1014 Ω and breakdown fields above 106 V/cm at 4.2 K. In addition to exhibiting standard FET characteristics, including gating to pinchoff, the devices showed significant negative differential resistance (NDR) in the saturation region.

Publisher

Springer Science and Business Media LLC

Subject

General Engineering

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Parallel conduction in GaAs heterostructures modified by low-energy ion exposure;Journal of Applied Physics;1996

2. Effects of low energy ion exposure on modulation-doped GaAs heterostructures;Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures;1993-11

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