Selective Titanium Silicide for Industrial Applications

Abstract

AbstractThe possibilities of using TiSi2 for contacts and interconnects in 0.25 μm and below design rule ICs are at present being investigated using the standard solid phase reaction (salicide) technique. Some problems still remain, such as phase transformation or dewettability over narrow lines. Over the last few years we have developed a TiSi2 selective CVD technique which is being used for 200 mm wafers in an industrial integrated cluster reactor. The system consists of two reaction chambers: one for Si epitaxy (and related alloys) and the other for TiSi2 deposition. The process sequence involves three main steps: (i) a wet chemical wafer cleaning, (ii) a selective silicon epitaxy for elevated source/drains to obtain minimum substrate consumption and (iii) the deposition of TiSi2 using the H2/SiH4 (or DCS)/TiCl4 gas system in the 650–750°C temperature range. The whole process time per wafer is shorter than 4 min. Selectivity, stoichiometric composition and resistivity of around 16 μmΩcm are obtained. The growth rate, uniformity, grain size and doping effects have been studied on single, polycrystalline, doped and undoped silicon. Device wafers have been used to compare the two processes, standard and CVD, obtaining electrical results such as lower series resistances, and a linewidth independent sheet resistance of down to 0.20 μm.