Efficient Synapse Memory Structure for Reconfigurable Digital Neuromorphic Hardware

Author:

Kim Jinseok,Koo Jongeun,Kim Taesu,Kim Jae-Joon

Funder

Ministry of Science, ICT and Future Planning

National Research Foundation of Korea

Publisher

Frontiers Media SA

Subject

General Neuroscience

Reference24 articles.

1. Truenorth: design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip;Akopyan;IEEE Trans. Comput. Aided Design Integr. Circ. Syst.,2015

2. Building block of a programmable neuromorphic substrate: a digital neurosynaptic core;Arthur,2012

3. Neurogrid: a mixed-analog-digital multichip system for large-scale neural simulations;Benjamin;Proc. IEEE,2014

4. Visual pattern extraction using energy-efficient “2-pcm synapse” neuromorphic architecture;Bichler;IEEE Trans. Electr. Dev.,2012

5. Design of silicon brains in the nano-cmos era: spiking neurons, learning synapses and neural architecture optimization;Cassidy;Neural Netw.,2013

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