Affiliation:
1. School of Microelectronics, Xidian University, Xi’an 710071, China
Abstract
With the rapid development of semiconductor technology, traditional equation-based modeling faces challenges in accuracy and development time. To overcome these limitations, neural network (NN)-based modeling methods have been proposed. However, the NN-based compact model encounters two major issues. Firstly, it exhibits unphysical behaviors such as un-smoothness and non-monotonicity, which hinder its practical use. Secondly, finding an appropriate NN structure with high accuracy requires expertise and is time-consuming. In this paper, we propose an Automatic Physical-Informed Neural Network (AutoPINN) generation framework to solve these challenges. The framework consists of two parts: the Physics-Informed Neural Network (PINN) and the two-step Automatic Neural Network (AutoNN). The PINN is introduced to resolve unphysical issues by incorporating physical information. The AutoNN assists the PINN in automatically determining an optimal structure without human involvement. We evaluate the proposed AutoPINN framework on the gate-all-around transistor device. The results demonstrate that AutoPINN achieves an error of less than 0.05%. The generalization of our NN is promising, as validated by the test error and the loss landscape. The results demonstrate smoothness in high-order derivatives, and the monotonicity can be well-preserved. We believe that this work has the potential to accelerate the development and simulation process of emerging devices.
Funder
Xidian University
Beijing Microelectronics Technology Institute
Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory
China National Key R&D Program
111 Project of China
National Natural Science Foundation of China
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference28 articles.
1. Woo, S., Jeong, H., Choi, J., Cho, H., Kong, J.T., and Kim, S. (2022). Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors. Electronics, 11.
2. Duarte, J.P., Khandelwal, S., Medury, A., Hu, C., Kushwaha, P., Agarwal, H., Dasgupta, A., and Chauhan, Y.S. (2015, January 14–18). BSIM-CMG: Standard FinFET compact model for advanced circuit design. Proceedings of the ESSCIRC Conference 2015—41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria.
3. BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control;Khandelwal;IEEE Trans. Electron Devices,2012
4. PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation;Gildenblat;IEEE Trans. Electron Devices,2006
5. Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors;Wang;IEEE Trans. Electron Devices,2021