Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors
-
Published:2023-05-28
Issue:6
Volume:14
Page:1138
-
ISSN:2072-666X
-
Container-title:Micromachines
-
language:en
-
Short-container-title:Micromachines
Author:
Jeon Juhee1ORCID, Cho Kyoungah1, Kim Sangsig1
Affiliation:
1. Department of Electrical Engineering, Korea University, 145 Anam-ro, Seoul 02841, Republic of Korea
Abstract
Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+–n–p–n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 μA/μm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10−15 J/bit for the write ‘1’ operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.
Funder
National Research Foundation of Korea Korean government Brain Korea 21 Plus Project Samsung Electronics
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference40 articles.
1. Edge computing: A survey;Khan;Future Gener. Comput. Syst.,2019 2. Capra, M., Peloso, R., Masera, G., Roch, M.R., and Martina, M. (2019). Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World. Future Internet, 11. 3. Steegen, A. (2015, January 17–19). Technology innovation in an IoT Era. Proceedings of the 2015 Symposium on VLSI Circuits (VLSI Circuits), Kyoto, Japan. 4. Park, J.M., Hwang, Y.S., Kim, S.W., Han, S.Y., Park, J.S., Kim, J., Seo, J.W., Kim, B.S., Shin, S.H., and Cho, C.H. (2015, January 7–9). 20 nm DRAM: A new beginning of another revolution. Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA. 5. 1T-1C Dynamic Random Access Memory Status, Challenges, and Prospects;Spessot;IEEE Trans. Electron Devices,2020
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|