1. Wann, H.-J., and Hu, C. (1993, January 5–8). A capacitorless DRAM cell on SOI substrate. Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, USA.
2. A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications;Kuo;IEEE Trans. Electron. Devices,2003
3. Ranica, R., Villaret, A., Fenouillet-Beranger, C., Malinge, P., Mazoyer, P., Masson, P., Delille, D., Charbuillet, C., Candelier, P., and Skotnicki, T. (2004, January 13–15). A capacitor-less DRAM cell on 75 nm gate length, 16 nm thin fully depleted SOI device for high density embedded memories. Proceedings of the IEDM Technical Digest, IEEE International Electron Devices Meeting, Washington, DC, USA.
4. A capacitor-less 1T-DRAM cell;Okhonin;IEEE Electron. Device Lett.,2002
5. Okhonin, S., Nagoga, M., Sallese, J.M., and Fazan, P. (2001, January 1–4). A SOI capacitor-less 1T-DRAM concept. Proceedings of the IEEE International SOI Conference, Durango, CO, USA.