Cohesive Properties of Bimaterial Interfaces in Semiconductors: Experimental Study and Numerical Simulation Using an Inverse Cohesive Contact Approach

Abstract

Examining crack propagation at the interface of bimaterial components under various conditions is essential for improving the reliability of semiconductor designs. However, the fracture behavior of bimaterial interfaces has been relatively underexplored in the literature, particularly in terms of numerical predictions. Numerical simulations offer vital insights into the evolution of interfacial damage and stress distribution in wafers, showcasing their dependence on material properties. The lack of knowledge about specific interfaces poses a significant obstacle to the development of new products and necessitates active remediation for further progress. The objective of this paper is twofold: firstly, to experimentally investigate the behavior of bimaterial interfaces commonly found in semiconductors under quasi-static loading conditions, and secondly, to determine their respective interfacial cohesive properties using an inverse cohesive zone modeling approach. For this purpose, double cantilever beam specimens were manufactured that allow Mode I static fracture analysis of the interfaces. A compliance-based method was used to obtain the crack size during the tests and the Mode I energy release rate (GIc). Experimental results were utilized to simulate the behavior of different interfaces under specific test conditions in Abaqus. The simulation aimed to extract the interfacial cohesive contact properties of the studied bimaterial interfaces. These properties enable designers to predict the strength of the interfaces, particularly under Mode I loading conditions. To this extent, the cohesive zone modeling (CZM) assisted in defining the behavior of the damage propagation through the bimaterial interfaces. As a result, for the silicon–epoxy molding compound (EMC) interface, the results for maximum strength and GIc are, respectively, 26 MPa and 0.05 N/mm. The second interface tested consisted of polyimide and silicon oxide between the silicon and EMC layers, and the results obtained are 21.5 MPa for the maximum tensile strength and 0.02 N/mm for GIc. This study’s findings aid in predicting and mitigating failure modes in the studied chip packaging. The insights offer directions for future research, focusing on enhancing material properties and exploring the impact of manufacturing parameters and temperature conditions on delamination in multilayer semiconductors.