An FPGA-Based Performance Analysis of Hardware Caching Techniques for Blockchain Key-Value Database

Abstract

The speedy advancement in wireless communication technologies provides considerable development to enable smart cities with applications such as Intelligent Transport Systems (ITS) and the Internet of Medical Things (IoMT). Blockchain is an emerging technology that provides a secure and distributed data storage mechanism useful for smart city applications. The full nodes in the Blockchain contain a record of all the transactions and data blocks of the Blockchain users. As the number of full nodes is less and the number of Blockchain users is high, there is a huge load on the full nodes for accessing and verifying the data by the Blockchain users. Efficient hardware caching techniques are needed to decrease the data access delay. In this paper, we implement different caching techniques on the Field-Programmable Gate Array (FPGA) Network Interface Card (NIC) and analyze their performance for the key-value store caching in the Blockchain. We design the 2-way and 4-way caching techniques on Block Random-Access Memory (BRAM) and compare them with the conventional direct-mapped caching technique in terms of cache hits and cache misses. The improvements in the hit ratio of the 2-way set-associative cache technique with respect to the direct-mapped cache technique for 10 K, 25 K, and 50 K addresses are 0.8%, 0.77%, and 1.67%, respectively. On the other hand, for the same sets of addresses, the hit rate improvement of the 4-way set-associative cache technique with respect to the direct-mapped cache technique is 0.92%, 2.01%, and 2.4%, respectively. The improvements in hit rate for large data sets show that 2-way and 4-way set-associative cache techniques perform better than the direct-mapped cache technique for caching systems.