Ultrathin Small Outline Package Key Techniques for High-Speed Chips with Multi-Leads

Abstract

The key technologies for the ultrathin small outline package (TSOP) of large-sized high-speed chips have been designed and developed in this paper. The designing techniques, such as a 25 µm precise positioning dice attaching technique, a lead frame unit structure without a base island, and a lead co-plane layout inside the frame, were developed. The TSO package outline with a large number of leads, a frame unit arrangement, and a frame distribution with a base island and without one were improved. The technological problems, including the reduction in thickness, wafer cutting, chip sticking bonding, and plastic sealing, were successfully solved. The designed large-sized package products have many advantages, such as high availability, low cost, high reliability, and a short production cycle. This package technique can be widely used in various intellectual application regions.