Metal-Induced Trap States: The Roles of Interface and Border Traps in HfO2/InGaAs

Author:

Do Huy-Binh1ORCID,Luc Quang-Ho2,Pham Phuong V.3,Phan-Gia Anh-Vu1,Nguyen Thanh-Son4ORCID,Le Hoang-Minh5,De Souza Maria Merlyne6ORCID

Affiliation:

1. Faculty of Applied Science, Ho Chi Minh City University of Technology and Education, 01 Vo Van Ngan Street, Ho Chi Minh City 700000, Vietnam

2. Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, 1001, Daxue Road, East District, Hsinchu 300093, Taiwan

3. Department of Physics, National Sun Yat-sen University, Kaohsiung 80424, Taiwan

4. Faculty of Fundamental Sciences, University of Architecture Ho Chi Minh City, 196 Pasteur St., Dist. 3, Ho Chi Minh City 700000, Vietnam

5. Faculty of electrical and electronics engineering, Ho Chi Minh City University of Technology and Education, 01 Vo Van Ngan Street, Ho Chi Minh City 700000, Vietnam

6. EEE Department, University of Sheffield, Sheffield S10 2TN, UK

Abstract

By combining capacitance–voltage measurements, TCAD simulations, and X-ray photoelectron spectroscopy, the impact of the work function of the gate metals Ti, Mo, Pd, and Ni on the defects in bulk HfO2 and at the HfO2/InGaAs interfaces are studied. The oxidation at Ti/HfO2 is found to create the highest density of interface and border traps, while a stable interface at the Mo/HfO2 interface leads to the smallest density of traps in our sample. The extracted values of Dit of 1.27 × 1011 eV−1cm−2 for acceptor-like traps and 3.81 × 1011 eV−1cm−2 for donor-like traps are the lowest reported to date. The density and lifetimes of border traps in HfO2 are examined using the Heiman function and strongly affect the hysteresis of capacitance–voltage curves. The results help systematically guide the choice of gate metal for InGaAs.

Funder

Ho Chi Minh City University of Technology and Education, Vietnam

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering

Reference60 articles.

1. Plasma Enhanced Atomic Layer Deposition Passivated HfO2/AlN/In0.53Ga0.47As MOSCAPs with Sub-Nanometer Equivalent Oxide Thickness and Low Interface Trap Density;Luc;IEEE Electron Device Lett.,2015

2. Effects of In-Situ Plasma-Enhanced Atomic Layer Deposition Treatment on the Performance of HfO2/In0.53Ga0.47As Metal–Oxide–Semiconductor Field-Effect Transistors;Luc;IEEE Electron Device Lett.,2016

3. Impact of AlN Interfacial Dipole on Effective Work Function of Ni and Band Alignment of Ni/HfO2/In0.53Ga0.47As Gate-Stack;Do;IEEE Trans. Electron Devices,2015

4. Investigation of Mo/Ti/AlN/HfO2 High-k Metal Gate Stack for Low Power Consumption InGaAs NMOS Device Application;Do;IEEE Electron Device Lett.,2017

5. Luc, Q.H., Fan-Chiang, C.C., Huynh, S.H., Huang, P., Do, H.B., Ha, M.T.H., Jin, Y.D., Nguyen, T.A., Zhang, K.Y., and Wang, H.C. (2018, January 18–22). First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs with Hf0.5Zr0.5O2 Ferroelectric Gate Stack. Proceedings of the 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, USA.

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