Pre-Computing Batch Normalisation Parameters for Edge Devices on a Binarized Neural Network
Author:
Phipps Nicholas12ORCID, Shang Jin-Jia12, Teo Tee Hui1ORCID, Wey I-Chyn2ORCID
Affiliation:
1. Engineering Product Development, Singapore University of Technology and Design, Singapore 487372, Singapore 2. Department of Electrical Engineering, Chang Gung University, Taoyuan City 333, Taiwan
Abstract
Binarized Neural Network (BNN) is a quantized Convolutional Neural Network (CNN), reducing the precision of network parameters for a much smaller model size. In BNNs, the Batch Normalisation (BN) layer is essential. When running BN on edge devices, floating point instructions take up a significant number of cycles to perform. This work leverages the fixed nature of a model during inference, to reduce the full-precision memory footprint by half. This was achieved by pre-computing the BN parameters prior to quantization. The proposed BNN was validated through modeling the network on the MNIST dataset. Compared to the traditional method of computation, the proposed BNN reduced the memory utilization by 63% at 860-bytes without any significant impact on accuracy. By pre-computing portions of the BN layer, the number of cycles required to compute is reduced to two cycles on an edge device.
Subject
Electrical and Electronic Engineering,Biochemistry,Instrumentation,Atomic and Molecular Physics, and Optics,Analytical Chemistry
Reference36 articles.
1. A Systematic Literature Review on Binary Neural Networks;Sayed;IEEE Access,2023 2. Chang, J., Chen, Y.H., Chan, G., Cheng, H., Wang, P.S., Lin, Y., Fujiwara, H., Lee, R., Liao, H.J., and Wang, P.W. (2020, January 16–20). 15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. Proceedings of the 2020 IEEE International Solid- State Circuits Conference—(ISSCC), San Francisco, CA, USA. 3. Chang, C.H., Chang, V., Pan, K., Lai, K., Lu, J.H., Ng, J., Chen, C., Wu, B., Lin, C., and Liang, C. (2022, January 3–7). Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond. Proceedings of the 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA. 4. Larq: An Open-Source Library for Training Binarized Neural Networks;Geiger;J. Open Source Softw.,2020 5. Simons, T., and Lee, D.J. (2019). A review of Binarized Neural Networks. Electronics, 8.
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