SLLB-DEVS: An Approach for DEVS Based Modeling of Semiconductor Lithography Load Balance

Abstract

In industrial applications, software related to computational lithography using a DP system method, which refers to how efficiently hardware resources are used, has a significant impact on performance. Because the amount of data to be processed per unit of time is comparatively large in the current semiconductor industry, the efficiency of hardware should be increased through job 12 scheduling by using the most efficient load balancing techniques possible. For efficient scheduling of the load balancer, these are necessary to predict the end time of a given job; this is calculated based on the performance of computing resources and the development of effective traffic distribution algorithms. Due to the high integration of semiconductor chips, the volume of mask exposure data has increased exponentially, the number of slave nodes is increasing, and most EDA tools require one license per DP node to perform a simulation. In this paper, in order to improve efficiency and reduce cost through more efficient load balancing scheduling, a new type of DEVS load balancing method was studied based on the existing industrial E-beam cluster model. The designed DEVS model showed up to four times the throughput of the existing legacy model for medium and large clusters when the BSF policy was applied.