Abstract
This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied. Compared to the conventional SRAM cell circuits, one possibility is adding redundant storage nodes by means of additional transistors. The strength and weakness of the SRAM cells in terms of various performance aspects—speed, area, power, stability, fault tolerance, etc.—according to the design approaches are compared analytically and discussed. The discussion concludes that, in the future, it is paramount to develop an SRAM cell design with a mitigated trade-off between read/write performance and SEU tolerance.
Subject
Fluid Flow and Transfer Processes,Computer Science Applications,Process Chemistry and Technology,General Engineering,Instrumentation,General Materials Science
Reference22 articles.
1. Single event upset (SEU) in SRAM;Int. J. Eng. Res. Appl.,2013
2. McLain, M.L., Barnaby, H.J., Esqueda, I.S., Oder, J., and Vermeire, B. (2009, January 26–30). Reliability of High Performance Standard Two-Edge and Radiation Hardened by Design Enclosed Geometry Transistors. Proceedings of the 2009 IEEE International Reliability Physics Symposium, Montreal, QC, Canada.
3. A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets;IEEE Trans. Device Mater. Reliab.,2016
4. Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model;J. Electron. Test.,2017
5. Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems;IEEE Trans. Nucl. Sci.,2006
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