Al2O3 Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices

Author:

Schilirò Emanuela1,Fiorenza Patrick1ORCID,Lo Nigro Raffaella1,Galizia Bruno1ORCID,Greco Giuseppe1ORCID,Di Franco Salvatore1,Bongiorno Corrado1,La Via Francesco1ORCID,Giannazzo Filippo1ORCID,Roccaforte Fabrizio1ORCID

Affiliation:

1. Consiglio Nazionale delle Ricerche, Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII 5, Zona Industriale, 95121 Catania, Italy

Abstract

Metal-oxide-semiconductor (MOS) capacitors with Al2O3 as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al2O3 is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO2 interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al2O3/SiO2 stacks show lower negative shifts of the flat band voltage VFB (in the range of about −3 V) compared with the conventional single SiO2 layer (in the range of −9 V). This lower negative shift is due to the combined effect of the Al2O3 higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO2. Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al2O3 layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al2O3 sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al2O3 obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps.

Funder

European project CHALLENGE

European Union (NextGeneration EU), through the MUR-PNRR projects SAMOTHRACE

iEntrance@ENL

Publisher

MDPI AG

Subject

General Materials Science

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