Simulation of a Low-Voltage Direct Current System Using T-SFCL to Enhance Low Voltage Ride through Capability

Abstract

Owing to the increasing penetration level of distributed energy resources (DER) and direct current (DC) load, the usage of low-voltage direct current (LVDC) systems has expanded to achieve efficient operations. However, because the LVDC system reaches the peak fault current at a faster rate than the alternating current (AC) system, a solution that protects the system components is necessary to maintain system integrity. It is required by the low-voltage ride-through (LVRT) that the DERs maintain their interconnections with the LVDC system and support fault recovery. In this study, a method is proposed to allow the application of the superconducting fault current limiter (SFCL) to reduce the fault current and enhance the LVRT capability. However, when the DER maintain a connection to support fault recovery, the conventional resistive-type SFCL must withstand the burden of high-temperature superconducting (HTSC) operation during fault state dependence on LVRT. Therefore, this study proposes a trigger-type SFCL to reduce the burden of the HTSC element and enhance the LVRT capability. The voltage sag related to the LVRT was improved owing to the SFCL. The proposed solution was confirmed using PSCAD/EMTDC, which is a commercial software.