Affiliation:
1. Department of Electronics and Electrical Engineering and Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu 300, Taiwan
Abstract
2D field-effect transistors (FETs) fabricated with transition metal dichalcogenide (TMD) materials are a potential replacement for the silicon-based CMOS. However, the lack of advancement in p-type contact is also a key factor hindering TMD-based CMOS applications. The less investigated path towards improving electrical characteristics based on contact geometries with low contact resistance (RC) has also been established. Moreover, finding contact metals to reduce the RC is indeed one of the significant challenges in achieving the above goal. Our research provides the first comparative analysis of the three contact configurations for a WSe2 monolayer with different noble metals (Rh, Ru, and Pd) by employing ab initio density functional theory (DFT) and non-equilibrium Green’s function (NEGF) methods. From the perspective of the contact topologies, the RC and minimum subthreshold slope (SSMIN) of all the conventional edge contacts are outperformed by the novel non-van der Waals (vdW) sandwich contacts. These non-vdW sandwich contacts reveal that their RC values are below 50 Ω∙μm, attributed to the narrow Schottky barrier widths (SBWs) and low Schottky barrier heights (SBHs). Not only are the RC values dramatically reduced by such novel contacts, but the SSMIN values are lower than 68 mV/dec. The new proposal offers the lowest RC and SSMIN, irrespective of the contact metals. Further considering the metal leads, the WSe2/Rh FETs based on the non-vdW sandwich contacts show a meager RC value of 33 Ω∙μm and an exceptional SSMIN of 63 mV/dec. The two calculated results present the smallest-ever values reported in our study, indicating that the non-vdW sandwich contacts with Rh leads can attain the best-case scenario. In contrast, the symmetric convex edge contacts with Pd leads cause the worst-case degradation, yielding an RC value of 213 Ω∙μm and an SSMIN value of 95 mV/dec. While all the WSe2/Ru FETs exhibit medium performances, the minimal shift in the transfer curves is interestingly advantageous to the circuit operation. Conclusively, the low-RC performances and the desirable SSMIN values are a combination of the contact geometries and metal leads. This innovation, achieved through noble metal leads in conjunction with the novel contact configurations, paves the way for a TMD-based CMOS with ultra-low RC and rapid switching speeds.
Funder
Ministry of Education (MOE) in Taiwan
National Science and Technology Council, Taiwan
Reference71 articles.
1. Improved subthreshold swing and short channel effect in FDSOI n-channel negative capacitance field effect transistors;Kwon;IEEE Electron Device Lett.,2017
2. Chan, T., Chen, J., Ko, P., and Hu, C. (1987, January 6–9). The impact of gate-induced drain leakage current on MOSFET scaling. Proceedings of the 1987 International Electron Devices Meeting, Washington, DC, USA.
3. VLSI limitations from drain-induced barrier lowering;Troutman;IEEE J. Solid-State Circuits,1979
4. Two-dimensional transition metal dichalcogenides as atomically thin semiconductors: Opportunities and challenges;Duan;Chem. Soc. Rev.,2015
5. CMOS design near the limit of scaling;Taur;IBM J. Res. Dev.,2002