Abstract
Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth is affected is not very dependent on the stack height.
Funder
National Research Foundation of Korea
IC Design Education Center
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference14 articles.
1. 3-D NAND Technology Achievements and Future Scaling Perspectives
2. CMOS scaling for high performance and low power-the next ten years
3. Comparison of Current 3D NAND Chip & Cell Architecture;Choe,2019
4. Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory;Fukuzumi;Proceedings of the 2007 IEEE International Electron Devices Meeting,2007
5. Analysis of performance/variability trade-off in Macaroni-type 3-D NAND memory;Congedo;Proceedings of the 2014 IEEE 6th International Memory Workshop (IMW),2014
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献