A Fast Recovery Vertical Superjunction MOSFET with n-Si and p-3C-SiC Pillars

Abstract

In the traditional SJ MOSFET structure, n/p pillars with the same doping concentrations in the drift region are introduced to decrease the on-resistance. However, SJ MOSFET will turn on the parasitic diodes due to fast reverse recovery, further inducing severe oscillation in the reverse recovery of the device and the corresponding adverse effect on the circuit. In this study, a fast recovery vertical superjunction (SJ) MOSFET with n-Si and p-3C-SiC pillars was studied. Unlike other structures, such as the 4H-SiC superjunction UMOSFET with a heterojunction diode or the ultra-low recovery charge cell-distributed Schottky contacts SJ-MOSFET with integrated isolated NMOS, we introduce a Schottky barrier diode (SBD) on the source contact at the top of the n-Si pillar in the SJ-MOSFET to improve the device reverse recovery. The simulation software TCAD Silvaco was utilized to simulate the device properties. Compared with the conventional Si SJ, the proposed Si/SiC SJ with the Schottky barrier diode (SBD) connected demonstrated a lower reverse recovery charge, which was reduced by 90.5%, respectively. The waveform of the reverse recovery current demonstrates that the electrons in the device are withdrawn from SBD during reverse recovery, preventing the opening of the parasitic diode in the SJ MOSFET. Finally, another structure is illustrated to decrease the gate capacitance by introducing a thin p-base layer between the gate metal and N-Si pillar so that it can improve the switching characteristics of devices. The open-loss and off-loss of the improved device were reduced by 33% and 42.3%, respectively.