Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory
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Published:2023-10-09
Issue:10
Volume:14
Page:1916
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ISSN:2072-666X
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Container-title:Micromachines
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language:en
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Short-container-title:Micromachines
Author:
You Kaikai12, Jin Lei12, Jia Jianquan12, Huo Zongliang12
Affiliation:
1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China 2. University of Chinese Academy of Sciences, Beijing 100049, China
Abstract
To satisfy the increasing demands for more word-line (WL) layers, the dual-deck even triple-deck architecture has emerged in 3D NAND Flash. However, the new reliability issues that occurred at the joint region of two decks became a severe challenge for developing multiple-deck technology. This work reported an abnormal reliability issue introduced by erasing disturbance of the dummy WLs at the joint region (Joint-DMYs) under multiple cycling. More specifically, after several erase cycling stresses, the increasing joint-DMY’s threshold voltage (Vt) due to the operational stress will finally result in additional disturbance to the adjacent data WLs. In this paper, we proposed this disturbance during erase originates from the backward injected electrons through FN tunneling based on our TCAD simulation result. Moreover, we also proposed an optimal erase scheme to reduce the backward electron injection and suppress the abnormal joint-DMY disturbance during the erase cycling.
Funder
National Key Research and Development Program of China
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
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