Abstract
Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis, combined with a TCAD characterization process. Furthermore, the proposed work analyzes the effect of a Static Timing Analysis (STA) methodology and the actual interconnection delay on SER evaluation. An analysis of the generated Single Event Multiple Transients (SEMTs) and the circuit operating frequency that are related to the SER estimation is also discussed. Various benchmarks, synthesized utilizing a 45 nm and 15 nm technology, are employed, and the experimental results demonstrate the SER variation as the device node scales down.
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4 articles.
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1. Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
2. SET Effects on Quasi Delay Insensitive and Synchronous Circuits;2023 IEEE European Test Symposium (ETS);2023-05-22
3. MOCAST 2021;Technologies;2022-07-20
4. Real-Time Design and Implementation of Soft Error Mitigation Using Embedded System;Journal of Circuits, Systems and Computers;2022-05-23