Rapid Processing of Wafer-Scale Anti-Reflecting 3D Hierarchical Structures on Silicon and Its Templation

Abstract

Hierarchically structured silicon (Si) surfaces with a combination of micro/nano-structures are highly explored for their unique surface and optical properties. In this context, we propose a rapid and facile electroless method to realize hierarchical structures on an entire Si wafer of 3″ diameter. The overall process takes only 65 s to complete, unlike any conventional wet chemical approach that often combines a wet anisotropic etching of (100) Si followed by a metal nanoparticle catalyst etching. Hierarchical surface texturing on Si demonstrates a broadband highly reduced reflectance with average R% ~ 2.7% within 300–1400 nm wavelength. The as-fabricated hierarchical structured Si was also templated on a thin transparent layer of Polydimethylsiloxane (PDMS) that further demonstrated prospects for improved solar encapsulation with high optical clarity and low reflectance (90% and 2.8%).