Novel Step Floating Islands VDMOS with Low Specific on-Resistance by TCAD Simulation

Abstract

A novel VDMOS with Step Floating Islands VDMOS (S-FLI VDMOS) is proposed for the first time in this letter, in order to optimize the breakdown voltage (BV) and the specific on-resistance (Ron,sp). The innovative terminal technology of Breakdown Point Transfer (BPT) is applied to S-FLI VDMOS, which transfers the breakdown point from the high electric field region to the low electric field region, and the S-FLI VDMOS structure uses multiple layers of charge compensation blocks to generate multiple electric field peaks in the drift region in order to optimize the electric field distribution. In the TCAD simulation, the BV of the proposed S-FLI VDMOS is improved to 326 V, which is higher than that of 281 V for the conventional Si VDMOS with the same drift region length of 15 μm, and the Ron,sp is reduced from 21.54 mΩ·cm2 for the conventional Si VDMOS to 7.77 mΩ·cm2 for the S-FLI VDMOS. Compared with the conventional Si VDMOS, the current density of the effective current conduction path is increased when the forward bias is applied to the proposed device.