Affiliation:
1. Faculty of Electronics Telecommunications and Informatics, Gdańsk University of Technology, 80-233 Gdańsk, Poland
2. School of Engineering and Computer Science, University of Hertfordshire, Hatfield AL10 9AB, UK
Abstract
This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.
Funder
National Science Centre of Poland
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering